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ispLSI 2096/A
In-System Programmable High Density PLD Features
* ENHANCEMENTS -- ispLSI 2096A is Fully Form and Function Compatible to the ispLSI 2096, with Identical Timing Specifcations and Packaging -- ispLSI 2096A is Built on an Advanced 0.35 Micron E2CMOS(R) Technology * HIGH DENSITY PROGRAMMABLE LOGIC -- -- -- -- -- 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs 96 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- -- -- -- -- -- --
Output Routing Pool (ORP) Output Routing Pool (ORP)
(R)
Functional Block Diagram
C7 A0
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
S ES IG N
Global Routing Pool (GRP)
B0 B1 B2 B3
Output Routing Pool (ORP)
DQ
A1
A2
GLB
Logic Array
DQ
B6
DQ
B5
DQ
A3 A4 A5 A6 A7
B4
Output Routing Pool (ORP)
D
0919/2096
fmax = 125 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation Delay
TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power
* IN-SYSTEM PROGRAMMABLE
Copyright (c) 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
U SE
-- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity
is pL
SI
20
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
96
-- In-System Programmable (ISPTM) 5V Only -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping
The ispLSI 2096 and 2096A are High Density Programmable Logic Devices. The devices contain 96 Registers, 96 Universal I/O pins, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096 and 2096A feature 5V insystem programmability and in-system diagnostic capabilities. The ispLSI 2096 and 2096A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on these devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...C7 (Figure 1). There are a total of 24 GLBs in the ispLSI 2096 and 2096A devices. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
E
FO
R
N
EW
Description
January 2002
2096_08
1
Output Routing Pool (ORP)
B7
Specifications ispLSI 2096/A
Functional Block Diagram
Figure 1. ispLSI 2096/A Functional Block Diagram
GOE 0 GOE 1 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64
Generic Logic Blocks (GLBs)
C7
C6
C5
C4
C3
C2
Output Routing Pool (ORP)
Input Bus
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1
EW
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7
A1
A2
Global Routing Pool (GRP)
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
D ES IG N
C1 C0
B7 B6 B5 B4
Megablock
Output Routing Pool (ORP)
Output Routing Pool (ORP)
S
I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
CLK 0 CLK 1 CLK 2
0917
Input Bus
Input Bus
A0
A3
R
N
SDO RESET ispEN
Output Routing Pool (ORP) Input Bus
FO
A4
A5
A6
A7
B0
B1
B2
B3
Output Routing Pool (ORP)
Input Bus
I/O 16 I/O 17 I/O 18 I/O 19
I/O 20 I/O 21 I/O 22 I/O 23
I/O 24 I/O 25 I/O 26 I/O 27
I/O 28 I/O 29 I/O 30 I/O 31
E
IN 2 SCLK/IN 3
I/O 32 I/O 33 I/O 34 I/O 35
I/O 36 I/O 37 I/O 38 I/O 39
I/O 40 I/O 41 I/O 42 I/O 43
I/O 44 I/O 45 I/O 46 I/O 47
The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise.
20
96
is pL SI
The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2096 and 2096A devices are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
U SE
Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2096 and 2096A device contains three Megablocks.
2
Y0 Y1 Y2
IN 5 IN 4
Specifications ispLSI 2096/A
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
SYMBOL
PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial
EW
DC Recommended Operating Condition
D ES IG N
MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1
UNITS pf pf
S
UNITS V V V V
Table 2 - 0005/2096
Vcc VIL VIH
TA = -40C to + 85C
SYMBOL
PARAMETER
96
E
TYPICAL 8 15
Capacitance (TA=25C, f=1.0 MHz)
FO
R
N
TA = 0C to + 70C
TEST CONDITIONS VCC = 5.0V, VI/O, IN = 2.0V VCC = 5.0V, VY = 2.0V
Table 2-0006a
Clock Capacitance
Data Retention Specifications
PARAMETER MINIMUM 20 10000 MAXIMUM - - UNITS Years Cycles
Table 2-0008A-isp
Data Retention
Erase/Reprogram Cycles
U SE
is pL SI
20
C1 C2
I/O and Dedicated Input Capacitance
3
Specifications ispLSI 2096/A
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V -125 Others 1.5V 1.5V See Figure 2
Table 2-0003/2096
Figure 2. Test Load
+ 5V R1
2 ns 3 ns
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
0213/2096
C
Table 2-0004/2096
DC Electrical Characteristics
SYMBOL
E
Over Recommended Operating Conditions
FO
R
N
EW
96
PARAMETER Output Low Voltage Output High Voltage
CONDITION
ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current
is pL SI
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) 3.5V VIN VCC 0V VIN VIL (Max.) 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fCLOCK = 1 MHz Commercial Industrial
D ES IG N
R2 C L*
MIN. - 2.4 - - - - - - - TYP. - - - - - - - 150 150
3
Device Output
S
0.4 - -10 10 -150 -150 -200 295 -
Test Point
MAX. UNITS V V A A A A mA mA mA
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
U SE
20
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using six 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC .
Table 2-0007/2096
4
Specifications ispLSI 2096/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 # COND. A A A - - - A - - - - A - B C B C - - 1 2 3 4 5 6 7 8 9
4 1
DESCRIPTION
-125 - -
3 1
-100 - - 100 77.0 100 6.5 - 10.0 13.0 - - - - -
-80 15.0 18.5
MIN. MAX. MIN. MAX. MIN. MAX. 7.5 10.0 - - - - - - - 10.0 - 12.0 12.0 7.0 7.0 - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock Clock Frequency with External Feedback ( tsu2 + tco1)
125 100 125 5.0 - 0.0 6.0 - 0.0 - - - - - 4.0 4.0 5.0
81.0 57.0 83.0 9.0 - 0.0 -
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Product Term OE, Enable 15 Product Term OE, Disable 16 Global OE, Enable 17 Global OE, Disable
EW
N
R
18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
FO
U SE
is pL SI
20
96
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
E
5
D ES IG N
- 4.0 5.0 - - - 13.5 - 15.0 15.0 9.0 9.0 - - 0.0 - 8.0 11.0 0.0 - 10.0 - - - - 6.0 6.0 4.5 6.0 0.0 - 6.5 - - - - 5.0 5.0
S
- - - - - 6.5 - 8.0 - 17.0 - 18.0 18.0 12.0 12.0 - -
Table 2-0030/2096
Specifications ispLSI 2096/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #
2
DESCRIPTION
-125
-100
-80
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - - - - - 0.2 1.5 1.3 - - - 0.5 2.2 1.7 - - - 1.8
UNITS
Inputs
21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Comb. Path Delay 24 4 Product Term Bypass Reg. Path Delay 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay
S
4.4 2.6 8.1 6.8 8.0 8.8 9.8 1.3 - - 0.4 1.6 8.6 9.0 10.2 2.0 0.5 2.0 10.0 4.6 4.6 7.4 3.6 3.6 11.4
tio tdin
GRP
20 Input Buffer Delay
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
Outputs
is pL SI
tob tsl toen todis tgoe
Clocks
20
torp torpbp
96
ORP
36 ORP Delay 37 ORP Bypass Delay
E
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
4.5 5.7 6.0 6.5 0.5 - - 0.2 1.1 4.8 7.3
5.0
EW N
0.8 3.0 - - - - 3.3 - - - - - - - 2.3 2.3 -
R
33 GLB Product Term Reset to Register Delay 35 GLB Product Term Clock Delay
FO
34 GLB Product Term Output Enable to I/O Cell Delay
0.8 0.3 1.2 10.0 3.2 3.2 3.8 2.3 2.3 6.9
38 Output Buffer Delay 39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. Clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
U SE
tgy0 tgy1/2 tgr
Global Reset
- 9.2 -
Table 2-0036/2096
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
6
D ES IG N
- 5.8 6.8 7.3 8.0 0.5 - - 0.3 1.3 6.1 8.6 7.1 1.4 0.4 1.6 10.0 4.2 4.2 4.8 2.7 2.7 - - 5.8 - - - - - - - 1.2 4.0 - - - - 4.1 - - - - - - - 2.7 2.7 - - 1.4 6.0 - - - - 5.6 - - - - - - - 3.6 3.6 5.6
Specifications ispLSI 2096/A
ispLSI 2096/A Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 GLB ORP I/O Cell
#21 I/O Delay #20
EW
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0,1 #43, 44 #42
N
tsu
th
Note: Calculations are based upon timing specifications for the ispLSI 2096/A-125L.
Table 2-0042B/2096
U SE
is pL SI
tco
= = = 9.3 ns =
Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20+ #22+ #35) + (#31) + (#36 + #38) (0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
20
= = = 2.6 ns =
Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20+ #22+ #35) + (#30) - (#20+ #22+ #26) (0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
96
E
= = = 3.5 ns =
Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20+ #22+ #26) + (#29) - (#20+ #22+ #35) (0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
FO
Derivations of tsu, th and tco from the Product Term Clock
7
R
D ES IG N
ORP Delay #36 #40, 41
0491/2000
I/O Pin (Input)
S
#38, 39
I/O Pin (Output)
Specifications ispLSI 2096/A
Power Consumption
Power consumption in the ispLSI 2096 and 2096A devices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax used. Figure 4 shows the relationship between power and operating speed.
300 250
ispLSI 2096/A
ICC (mA)
200 150 100 50 0 20 40 60 80
100 120 140
fmax (MHz)
ICC can be estimated for the ispLSI 2096/A using the following equation: ICC(mA) = 20 + (# of PTs * 0.67) + (# of nets * Max freq * 0.011) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
is pL SI
20
96
E
FO
R
Notes: Configuration of six 16-bit counters Typical current at 5V, 25C
N
EW
U SE
8
D ES IG N
0127/2096
S
Specifications ispLSI 2096/A
Pin Description
NAME
I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE 0, GOE 1 IN 2, IN 4, IN 5 ispEN
PQFP & TQFP PIN NUMBERS
21, 27, 34, 40, 52, 58, 66, 72, 85, 91, 98, 104, 117, 123, 2, 8, 64, 51, 18 22, 28, 35, 41, 53, 59, 67, 73, 86, 92, 99, 105, 118, 124, 3, 9, 114 84, 110 23, 29, 36, 42, 54, 60, 68, 74, 87, 93, 100, 106, 119, 125, 4, 10, 24, 30, 37, 43, 55, 61, 69, 75, 88, 94, 101, 107, 120, 126, 5, 11, 25, 31, 38, 44, 56, 62, 70, 76, 89, 95, 102, 108, 121, 127, 6, 12, 26 32 39 45 57 63 71 77 90 96 103 109 122 128 7 13
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Global Output Enables input pins.
Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN0 also is used as one of the two control pins for the isp state machine. When ispEN is high, it functions as a dedicated input pin.
SDI/IN 02
20
46
SDO SCLK/IN 32
50
E
20
96
78
RESET Y0, Y1, Y2 GND VCC NC1
19 15 1, 97, 16, 83, 17, 112 48,
80
is pL SI
33,
49, 113 111,
65,
82,
14,
47,
79,
115,
U SE
1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability.
FO
MODE/IN 12
Input - This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. When ispEN is high, it functions as a dedicated input pin. Output - When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated input pin. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device.
81,
Ground (GND) VCC
116
No Connect.
R
N
EW
Dedicated input pins to the device.
D ES IG N
Table 2-0002-2096
9
S
Specifications ispLSI 2096/A
Pin Configuration
ispLSI 2096/A 128-pin PQFP and TQFP Pinout Diagram
I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 NC1 NC1 GOE 1 VCC GND NC1 IN 5 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND
U SE
1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability.
0124A-2096
GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 2MODE/IN 1 1NC VCC GND SDO IN 2 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GOE 0
is pL SI
GND I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 1NC Y0 VCC GND ispEN RESET 2SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
20
96
E
FO
Top View
10
R
ispLSI 2096/A
N
EW
D ES IG N
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
S
I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 4 Y1 VCC GND Y2 NC1 SCLK/IN 32 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND
Specifications ispLSI 2096/A
Part Number Description
ispLSI XXXXX - XXX
Device Family Device Number 2096 2096A Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 81 MHz fmax
X
X
X
Grade Blank = Commercial I = Industrial Package T = TQFP Q = PQFP Power L = Low
212-80Cisp/2096
ispLSI 2096/A Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 125 125 100 100 81 ispLSI 81 125 125 100 100 81 81 tpd (ns) 7.5 7.5 10 10 15 15 7.5 7.5 10 10 ORDERING NUMBER
EW
N
ispLSI 2096A-125LQ128 ispLSI 2096A-100LQ128
R
ispLSI 2096A-125LT128
FO
ispLSI 2096A-100LT128 ispLSI 2096A-80LQ128 ispLSI 2096A-80LT128 ispLSI 2096-125LQ ispLSI 2096-125LT ispLSI 2096-100LQ ispLSI 2096-100LT ispLSI 2096-80LQ ispLSI 2096-80LT
E
96
20
15
is pL SI
15
INDUSTRIAL
ORDERING NUMBER ispLSI 2096A-80LQ128I ispLSI 2096A-80LT128I ispLSI 2096-80LQI ispLSI 2096-80LTI PACKAGE 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP
Table 2-0041D/2096
FAMILY
fmax (MHz) 81 81 81 81
tpd (ns) 15 15 15 15
U SE
ispLSI
11
D ES IG N
PACKAGE 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP
Table 2-0041B/2096
S

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